The present invention relates to a digital noise erasing method executed with a circuit of an efficient scale for erasing noise contained in time-series digital input signals regardless of signal retaining time.
Input signals received in time series include signals indicating ON/OFF states generated by relays, etc., and direct current dial signals generated by telephone units. When such time-series signals are detected or received, errors may frequently be detected due to noise generated by chattering, etc., at a relay joint, but disappearing within a predetermined time period. That is, after a signal inputted in time series turns from "0" (OFF) to "1" (ON), a "0" (OFF) state is generated for a short time. If such noise is received as is, control is executed incorrectly.
In the prior art technologies, a detecting signal for detecting a change in a digital input signal is generated together with an extracting signal for extracting the digital input signal according to a clock signal, and extracted signals are stored in separate memories. The digital input signals are not outputted as noise (erased) if they become changed before being stored as the same signals ("0s" or "1s")
in a predetermined number of memories. The input signals are outputted as accepted data if the same signals ("0s" or "1s") are stored without any change in a predetermined number of memories.
FIG. 1 shows the circuit configuration of a prior art device for erasing noise according to the above described method.
First, d.sub.in 100 applies digital input signals ("1" or "0") to a distributing circuit 110. The distributing circuit 110 is connected to n 1-bit memories 120 (120-1-120-n). The distributing circuit 110 distributes the digital input signals d.sub.in according to a clock signal 170 and sequentially stores them in the memories 120.
The n memories 120 are connected to a comparator 130. The comparator 130 sequentially determines whether or not there is a change in the digital signals ("1" or "0") stored in the memories 120, and outputs a signal 180 to indicate that a change is detected". The outputted signal 180 is a selection signal for a selector 140. The selector 140 is connected to the n-th memory 120-n and to a memory 150 provided separately, and outputs the value of either memory 120-n or 150 as an output value d.sub.on 160. The output from the selector 140 is connected to the memory 150 and the value outputted from the selector is stored in the memory 150.
That is, in the initial state, the first digital input signal value ("1" or "0") is set in the memory 150. Then, the following digital input signal values are sequentially stored in the memories 120 (120-1-120-n). Each time an input signal is stored in one of the memories 120, the comparator compares the value currently stored in this memory 120 with the value previously stored. If a change is detected, a selection signal 180 indicating "a change is detected" is outputted. Then the value stored in the memory 150 is selected and outputted as d.sub.on 160. If the digital input signal values stored in all of the memories 120 are all equal, the selection signal 180 indicates "no changes" when the comparator finishes comparing the values in memory 120-n and the memory 120-(n-1). If the selection signal 180 indicates "no changes", the selector 140 selects the value stored in memory 120-n, outputs it as d.sub.on 160, and stores it in the memory 150.
In the above described circuit configuration, inputted signals are determined to be noise and are erased unless n equal signals are inputted. The number n of the memories 120 is set as the noise erasure time (the maximum time of a signal to be erased as noise). That is, if a signal having a clock signal cycle of 250 .mu.s and a retaining time equal to or less than 14 ms is defined as noise, a total of 56 units (that is, 56 bits) of memories 120 are required.
As described above, in the prior art technology, sufficient memories for storing a predetermined number of signals (having a capacity for a predetermined time period) are required. Therefore, if a longer noise erasure time is set, the memory capacity must be larger. That is, since the circuit is built in an input interface LSI, etc., of a system which processes digital input signals, a large memory causes the problem that the digital unit must be large and uneconomical.
Besides, a system in which noise erasure time can be changed must have a large memory capacity and the circuit must be modified as necessary, thus making the method troublesome.